1. Technical Field
The disclosure relates generally to semiconductor fabrication, and more particularly, to a method of forming for reducing pattern loading for a doped epitaxial process and a resulting semiconductor structure.
2. Background Art
Epitaxial layers or films are used in a wide variety of semiconductor devices. For example, epitaxial layers are advantageous in p-type field effect transistors (PFETs) using silicon germanium substrates in which parasitic features require doping with phosphorous and carbon, or arsenic and carbon, to create the appropriate compressive strain over the source/drain regions in the substrate. In order to create epitaxial layers having adequate defect-free thicknesses at current technology nodes, e.g., the 22 nm node, an iterative deposition and etching process is used. During deposition of the epitaxial layer, only a certain thickness grows defect free, e.g., 50-100 Angstroms (Å). After a thickness beyond that defect-free amount has been deposited, an etch process is used to remove any defective thickness. This process is repeated, for example, 20-30 times to achieve the target thickness.
One challenge with this process, as illustrated in FIG. 1, is that it results in very large differences in thicknesses of the epitaxial layers between the smallest features (T1) on a substrate which may be, e.g., D=1-2 nanometers, apart, and the largest features on the substrate (T2) which may be, e.g., nD=7-9 nanometers, apart. This problem is referred to as “pattern loading” due to the different thickness growth based on different substrate feature patterns. The difference in thickness may be as much as, for example, 25%. As a result of this situation, a minimum feature size exists, e.g., D=800 Angstroms, at which this process cannot be used due to the inability to create an adequately uniform thickness of epitaxial layer across the substrate. For example, the minimum feature size may be based on what is necessary or proper for downstream processing such as replacement metal gate (RMG) processing. In this case, the epitaxial layers have an upper limit on the thickness anywhere on the wafer to avoid encroachment of the source-drain regions during polysilicon or other dummy gate material removal from a gate area that will be later re-filled with a metal.